DIT is a parameter that represents the density interface traps that limit the mobility of electrical carriers in the multilayer wafers, and carrier mobility has a key influence on the electrical performance of a multilayer wafer. As an example, traps represented by DIT values at a BOX/active layer interface of a SOI wafer affect the carrier mobility in the active layer. It has been shown that a lower DIT is associated with a higher carrier mobility.
Therefore, since it is desirable to increase the mobility of electrical carriers in the active layer of a multilayer semiconductor wafer, it is desirable to minimize DIT values at interfaces between active layers and adjacent layers in the wafer. In the case of SOI-type wafers comprising an active layer (e.g., Si) covering an insulating layer (e.g. Si oxide), it is desirable to reduce DIT values at the interface between the active surface layer and the buried oxide layer. Similarly, it is desirable to reduce the variability of DIT values among the multilayer wafers of a group of wafers, i.e., a group of wafers manufactured under the same conditions in a wafer manufacturing facility.
It is known to carry out low temperature thermal treatment of SOI-type wafers in order to reduce DIT and its variability in the wafer. Such treatments are carried out at temperatures up to 600° C. for durations between 30 and 120 min. in an atmosphere which is neutral, or which contains only a small amount of hydrogen (e.g. 2% H2 in a N2 or Ar atmosphere). Such treatment is referred to as a “Forming Gas Anneal” (FGA). See, e.g., Scholberg-Henriksen et al. Oxide Charges Induced by Plasma Activation for Wafer Bonding, Sensors and Actuators A 102 (2002), 99-105.
It has been observed that when a FGA treatment is carried out on a wafer comprising more than one layer, such treatment reduce DIT values only at the first interface located under the surface of the wafer (“interface” being here understood as the delimitation between two adjacent layers). In this respect, if a capping oxide layer which covers the surface of a Si wafer, the above-mentioned article discloses reducing DIT only at the interface between the capping oxide layer and the underlying Si layer.
Therefore, a FGA treatment could be carried out for reducing the DIT at the interface between the active layer and the underlying oxide layer in a SOI-type wafer, but this FGA treatment would not be effective if wafer is covered by a capping oxide layer. Reduction of DIT at the interface between the active layer and the underlying layer, which is desired, would not be achieved or expected. Capping oxide layers having a thickness from 100 to 3000 Angströms (e.g. 2000 Angströms) are usually present over the surface of these wafer during the intermediate and final stages of the manufacturing process, and are removed only at the end of the process.
Indeed, tests conducted by the inventors have shown that a FGA carried out on a SOI wafer covered with an oxide layer of 2000 Angströms has no effect on the DIT at the interface between the active layer and the underlying buried oxide layer. FGA conditions tested included exposure to 450° C. for 90 min. in an argon atmosphere containing 2% hydrogen. Therefore, FGA treatment does not appear as a solution to reducing DIT at the interface between the active layer and the underlying layer in the presence of a capping layer.
Alternatively, a FGA treatment could be performed after all manufacturing steps have been carried out on the SOI-type wafer, including the steps of removing the capping oxide on the wafer. But such treatment would mean adding another lengthy treatment at the end of the manufacturing process of the wafer, which is of course not desired.
It is also possible to conduct a FGA treatment during early stages of the manufacturing of a SOI-type wafer. For example, such early FGA could be carried out on a “top” substrate to be used in a SMART-CUT® layer transfer method, before the bonding of the top substrate with a base substrate. Although, this could reduce DIT at the interface between an active layer and an adjacent insulating (e.g. oxide) layer, reductions are not observed in practice. DIT is a temperature-sensitive parameter, and subsequent processing steps (bonding, transfer, stabilization, . . . ) include high temperature treatments which change the values of DIT obtained through the early FGA to less desirable values.
Thus, there is a need for a method which allows reducing the DIT and its variability in a multilayer wafer, without requiring a significant additional processing time of the wafer.